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Ordering number: EN*4300
LC86E6032
CMOS IC
LC86E6032 8-Bit Single-Chip Microcontroller Preliminary Overview
The LC86E6032 microcontroller is a CMOS 8-bit single chip microcontroller with UVEPROM for LC866000A series. This microcontroller has the same functions and pin assignment as for the LC866000A series mask ROM version, and a 32K-byte EPROM. Program data is rewritable. It is suitable for program developments.
Package Dimensions
unit : mm
3126-DIC64S
[LC86E6032]
Features
(1) Option switching using EPROM data The optional functions of the LC866000A series can be specified using EPROM data. LC86E6032 can be checked the functions of trial piece using the mass production board. (2) Internal 32K-byte UVEPROM 32K-byte UVEPROM (ultraviolet erasable and programmable ROM) is built in. This corresponds to LC866032B/28B/24B/20A/16A/12A/08A. (3) The pin compatible with mask ROM version (4) Factory shipment DIC-64S QFC-64E (Under development)
SANYO : DIC64S unit : mm
3152-QFC64E
[LC86E6032]
SANYO : QIC64E
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters SANYO Electric Co., Ltd. Semiconductor LSI Div. Microcomputer Development Dep.
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
D3098HA (II)/6232JN No. 4300-1/19
LC86E6032
Notice for Use
LC86E6032 is provided for the program development and checking the function of LC866000A series. At using, take notice of the followings. (1) Reset It is necessary to be sure to go into `L' level and hold for 200 s to reset terminal (RES) after power supplied voltage has been over inferior limit of supply voltage. The option is specified until 3ms after going into `H' level to reset terminal by degrees. The program is executed from 00H of program counter. The output form of all ports are N-channel open-drain while `L' level to reset terminal. (2) Option The LC86E6032 uses 256 bytes addressed 7F00H to 7FFFH in program memory as option data area. This area does not affect the execution of program but means that the LC866032A program memory is 32512 bytes addressed 0000H to 7EFFH. The option data is specified by the option-setting program "SU866000.EXE". The specified option data is linked to the program area by linkage editor "L866000.EXE". (3) ROM space
7FFFH 7F00H 7EFFH 6FFFH 5FFFH 4FFFH 3FFFH 2FFFH 1FFFH
Option data Option data area 256 bytes
Option Option Data Data Area
Option Option Data Area Data Area
Option Option Data Area Data Area
Option Option Data Area Data Area
Option Option Data Area
Option Option Data Area
Program Area 32K
Program Area 28K LC866028B
LC86E6032
Program Area 24K LC866024B
Program Area 20K LC866020A
Program Area 16K LC866016A
Program Area 12K LC866012A
Program Area 8K LC866008A
0000H LC866032B
Item Operating temperature range (Topr) Output form of port at reset Output form of segment S0/T0 to S6/T6 S7/T7 to S15/T15 S16 to S23 S24 to S29 Operating supply voltage range (VDD)
(4) Points of difference LC86E6032 and LC866000A series (mask ROM version)
LC866032B/28B/24B/20A/16A/12A/08A -30C to +70C Output form specified by option data Pulldown resistance: Provided/ Not provided Specified by option Provided (fixed) Specified by option Specified by option 2.5 to 6.0V +10C to +40C Open-drain output Pulldown resistance Not provided Provided (fixed) Provided (fixed) Not provided 4.5 to 6.0V
No. 4300-2/19
LC86E6032
Option
A kind of option corresponding LC86E6032
Option types Input/output form of input/output ports Pins, Circuits Port 0 (specified in a bit) 1. Input Output 2. Input Output 1. Input Output 2. Input Output Contents of option :No Pullup MOS Transistor :N-channel open-drain :Pullup MOS Transistor :CMOS :Programmable pullup MOS Transistor :N-channel open-drain :Programmable pullup MOS Transistor :CMOS
Port 1 (specified in a bit)
Pullup MOS Transistor of input port
Port 7 (specified in a bit)
1. No Pullup MOS Transistor 2. Pullup MOS Transistor
A kind of option not corresponding LC86E6032
Option types Pulldown resistance of high voltage withstand output terminal Pins,Circuits S0/T0 to S6/T6 S16 to S29 (specified in a bit) Contents of option 1. Pulldown resistance 2. No Pulldown resistance
How to Use
(1) Specification of options LC86E6032 must be programmed after specifying option data. The option is specified by "SU866000.EXE". The specified option file and the file created by our macro assembler "M866000.EXE" are linked by our linkage loader "L866000.EXE" which creates .HEX file, then the option code is put in the option specifed area (7F00H to 7FFFH) of its .HEX file. (2) How to write data to EPROM When writing data that was created by the linker to the LC86E6032, a general-purpose EPROM programmer can be used by using special write conversion boards (W86EP6032D, W86EP6032Q). * Recommended EPROM programmers
Supplier Advantest Andou AVAL Minato Electronics EPROM programmer R4945, R4944, R4943 AF-9704 PKW-1100, PKW-3000 MODEL 1890A
* "27512 (Vp-p = 12.5 V) Intel high-speed programming" mode should be used. The address must be set to "0000H to 7FFFH" and the jumper (DASEC) must be set 'OFF' at programming. (3) How to use the data security function "Data security" is a function to prevent the EPROM data from being read. Instructions on using the data security function: 1. Set the jumper (DASEC) of the attachment 'ON'. 2. Attempt to program the EPROM. The EPROM programmer displays an error. The error is a result of normal activity of the data security feature, and does not indicate a problem with the programmer or the LSI. Notes * The data security function is not carried out when the data of all address contain 'FF' at step 2 above. * Data security cannot be executed when the sequential writing operation of programming "BLANK=>PROGRAM=>VERIFY" is used at step 2 above. * Set the jumper 'OFF' after the execution of data security.
No. 4300-3/19
LC86E6032
(4) Erasing data Use a general-purpose EPROM eraser to erase the written data. (5) Shielding The UVEPROM (ultraviolet erasable programmable ROM) is incorporated in the IC. Cover the window of the IC with a seal in use.
Data security
Data security 1Pin 1 mark pin mark of LSI
OFF
ON
OFF
OFF ON
ON
OFF ON
Pin 1
Data security OFF
1 pin Pin 1
W86EP6032Q
Not security OFF Data data security
W86EP6032D
No. 4300-4/19
LC86E6032
Pin Assignment
VSS
VDD
Top view
Pin Assignment
VSS
VDD
Top view
No. 4300-5/19
LC86E6032
System Block Diagram
Interrupt control
IR
PLA
A15 to A0 D7 to D0 TA CE OE DASEC VDDVPP
Standby control
EPROM control
RC X'tal
Clock generator
CF
EPROM(32KB) PC
Base timer SIO0 SIO1
Bus interface Port 1 Port 7 Port 8 Bus
ACC B register C register
Timer 0 Timer 1 ADC INT0 to INT3 Noise filter Real-time service XRAM (128 bytes) VFD controller
ALU
Bus
PSW RAR RAM Stack pointer Port 0 Watchdog timer
High voltage output
No. 4300-6/19
LC86E6032
Pin Description
Pin name VSS VDD VP I/O -- -- -- Function description Power supply pin (-) Power supply pin (+) Power supply pin (-) (Power supply for VFD display drive output) (Power supply for pull-down resistor) Power supply pin (+) * 8-bit input/output port * Input/output specification can be made for 4-bit unit. * Input for HOLD release * Input for port 0 interrupt * 8-bit input/output port * Data direction can be specified for each bit. * Other pin functions P10 : SIO0 data output P11 : SIO0 data input/ bus input/output P12 : SIO0 clock input/output P13 : SIO1 data output P14 : SIO1 data input/ bus input/output P15 : SIO1 clock input/output P16 : Buzzer output P17 : Timer 1 output (PWM output) * 4-bit input port * Other pin functions P70 : INT0 input/HOLD release/N-channel transistor output for watchdog timer. P71 : INT 1 input/HOLD release. P72 : INT 2 input/timer 0 event input. P73 : INT 3 input with noise filter/timer 0 event input. * Interrupt received format, vector address. Rising Falling Rising & falling Disable Disable Enable Enable High level Enable Enable Disable Disable * Pull-up resistor : Provided/Not provided * Output form : CMOS/ N-channel open-drain. Output form : CMOS/ N-channel open-drain Data input/output * D0 to D7 Power for programming Option Function in PROM mode
VDDVPP PORT0 P00 to P07
-- I/O
PORT1 P10 to P17
I/O
PORT7 P70 P71 to P73 I/O I
* Pull-up resistor : Provided/Not provided Input of PROM control signal * DASEC (*1) * OE (*2) * CE (*3)
Low level Enable Enable Disable Disable
Vector
INT0 INT1 INT2 INT3 PORT8 P80 to P83 S0/T0 to S6/T6 S7/T7 to S15/T15 I
Enable Enable Enable Enable
Enable Enable Enable Enable
03H 0BH 13H 1BH
* 4-bit input port * Other functions AD input port (4 port pins) Output for VFD display controller Segment/timing common output Output for VFD display controller Segment/timing common output Output with built-in pull-down resistor *S14/T14 : TA (*4) *S15/T15 : A14 (*5) Continued on next page.
O O
No. 4300-7/19
LC86E6032
Continued from preceding page. Pin name S16 to S23 I/O O Function description Output for VFD display controller Segment output Output with built-in pull-down resistor Output for VFD display controller Segment output Reset pin Test pin Should be left open. Input pin for 32.768 kHz crystal oscillation When not used, connect to VDD. Output pin for 32.768 kHz crystal oscillation When not used, should be left open. Input pin for ceramic resonator oscillation Output pin for ceramic resonator oscillation Option Function in PROM mode Address input *A13 to A0
S24 to S29 RES TEST1 XT1 XT2 CF1 CF2
O I O I O I O
*1 *2 *3 *4 *5
Memory select input for data security Output enable input Chip enable input TA PROM control signal input A14 Address input
* All of port options can be specified in bit unit. * A state of pins at reset.
Pin name Ports 0,7 Port 1 Pin name S0/T0 to S15/T15 S16 to S29 Input/output mode Input Input A state of pullup resistor specified at pullup option Fixd pullup resistor exsists Programmable pullup resistor OFF
A state of P-channel transistor P-channel transistor OFF P-channel transistor OFF
No. 4300-8/19
LC86E6032
Specification 1. Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Symbol Pins Conditions VDD[V] Maximum supply voltage Input voltage VDD max VI(1) VDD,VDDVPP * P 71, 72, 73 * Port 8 * RES VP * S0/T0 to S15/T15 * S16 to S29 Ports 0, 1,P 70 Ports 0, 1 S0/T0 to S15/T15 S16 to S29 Port 0 Port 1 * S0/T0 to S15/T15 * S16 to S29 Ports 0, 1 P70 Port 0 Port 1,P70 DIC64S QFC64E * CMOS output * At each pin At each pin At each pin Total of all pins Total of all pins Total of all pins At each pin At each pin Total of all pins Total of all pins Ta = +10C to +40C Ta = +10C to +40C VDD = VDDVPP min -0.3 -0.3 Ratings typ max +7.0 VDD+0.3 V Unit
VI(2) Output voltage Input/output voltage Highlevel output current Peak output current VO VIO IOPH(1) IOPH(2) IOPH(3) Total output current IOAH(1) IOAH(2) IOAH(3) Lowlevel output current Peak output current Total output current Allowable power dissipation Operating temperature range Storage temperature range IOPL(1) IOPL(2) IOAL(1) IOAL(2) Pd max(1) Pd max(2) Topr Tstg
VDD-45 VDD-45 -0.3 -4 -30 -15 -10 -10 -130
VDD+0.3 VDD+0.3 VDD+0.3 mA
20 15 -30 40 760
To be determined after evaluation
mW
+10 -65
+40 150
C
No. 4300-9/19
LC86E6032
2. Allowable Operating Conditions at Ta = +10C to +40C, VSS = 0 V
Parameter Symbol Pins Conditions VDD[V] Operating supply voltage range HOLD voltage VDD VHD VDD VDD 0.98 s tCYC tCYC 400 s * When in HOLD mode * RAM and registers retain previous data. 4.5 to 6.0 (Schmitt) Output disable Output disable 4.5 to 6.0 min 4.5 2.0 Ratings typ max 6.0 6.0 V Unit
Pulldown supply voltage Input high-level voltage
VP VIH(1) VIH(2)
VP Port 0
-35 0.4VDD +0.9
VDD VDD VDD
* Port 1 * P72, 73 (Schmitt) * P70 Port input/interrupt. * P71 * RES (Schmitt) P70 Watchdog timer * Port 8 Port 0 (Schmitt)
4.5 to 6.0 0.75VDD
VIH(3)
Output N-channel transistor OFF
4.5 to 6.0 0.75VDD
VDD
VIH(4) VIH(5) Input low-level voltage VIL(1) VIL(2) VIL(3)
Output N-channel transistor OFF
4.5 to 6.0
0.9VDD
VDD VDD 0.2VDD 0.25VDD 0.25VDD
4.5 to 6.0 0.75VDD Output disable Output disable N-channel transistor OFF 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 V SS VSS VSS
* Port 1 * P72, 73(Schmitt) * P70 Port input/interrupt. * P71 * RES (Schmitt) P70 Watchdog timer * Port 8
VIL(4) VIL(5) Operation cycle time Oscillation frequency range (Note 1) tCYC FmCF(1)
N-channel transistor OFF
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
VSS VSS 0.98 11.76 12
0.8VDD -1.0 0.25VDD 400 12.24 s MHz
CF1, CF2
* 12 MHz (ceramic 4.5 to 6.0 resonator oscillation). * Refer to Figure 1. * 3 MHz (ceramic 4.5 to 6.0 resonator oscillation). * Refer to Figure 1. RC oscillation 4.5 to 6.0 4.5 to 6.0
FmCF(2)
CF1, CF2
2.94
3
3.06
FmRC FsXtal XT1, XT2
0.4
0.8 32.768
2.0 kHz
* 32.768 kHz (crystal oscillation). * Refer to Figure 2.
Oscillation stable time period (Note 1)
tmsCF(1)
CF1, CF2
* 12 MHz (ceramic 4.5 to 6.0 resonator oscillation). * Refer to Figure 3. * 3 MHz (ceramic 4.5 to 6.0 resonator oscillation). * Refer to Figure 3. * 32.768 kHz (crystal oscillation). * Refer to Figure 3. 4.5 to 6.0
0.02
0.2
ms
tmsCF(2)
CF1, CF2
0.1
1
tssXtal
XT1, XT2
1
1.5
s
(Note 1) Refer to Table 1 and Table 2 for the oscillation constants. No. 4300-10/19
LC86E6032
3. Electrical Characteristics at Ta= +10C to +40C , VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Input high-level current IIH(1) * Port 1 * Port 0 without pull-up MOS transistor * Output disable * Pull-up MOS transistor OFF. * VIN = VDD (including off-state leak current of output transistor) VIN= VDD 4.5 to 6.0 1 4.5 to 6.0 min Ratings typ max 1 A Unit
IIH(2)
* Port 7 without pull-up MOS transistor * Port 8 * RES * Port 1 * Port 0 without pull-up MOS transistor
IIH(3) Input low-level current IIL(1)
VIN = VDD
4.5 to 6.0 -1
1
4.5 to 6.0 * Output disable * Pull-up MOS transistor OFF. * VIN = VSS (including off-state leak current of output transistor) VIN = VSS 4.5 to 6.0
IIL(2)
* Port 7 without pull-up MOS transistor * Port 8 * RES * Ports 0, 1 at CMOS output S0/T0 to S15/T15
-1
IIL(3) Output high-level voltage VOH(1) VOH(2) VOH(3) VOH(4)
VIN = VSS IOH = -1.0 mA IOH = -0.1 mA IOH = -20 mA
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
-1 VDD-1 VDD-0.5 VDD-1.8 VDD-1 V
* IOH= -1.0 mA 4.5 to 6.0 * The current of any unmeasurement pin is not over 1 mA. S16 to S29 IOH = -5 mA 4.5 to 6.0
VOH(5) VOH(6)
VDD-1.8 VDD-1
* IOH= -1.0 mA 4.5 to 6.0 * The current of any unmeasurement pin is not over 1 mA. Ports 0,1 IOL = 10 mA * IOL = 1.6 mA * The total current of the Ports 0,1 is not over 40 mA 4.5 to 6.0 4.5 to 6.0
Output low-level voltage
VOL(1) VOL(2)
1.5 0.4
VOL(3) Pull-up MOS transistor resistor Output off-state leak current Rpu IOFF(1)
P70 * Ports 0, 1 * Port 7 * S0/T0 to S6/T6 * S24 to S29 (Without pulldown resistor)
IOL = 1 mA VOH = 0.9 VDD * Output P-channel transistor OFF. * VOUT= Vss * Output P-channel transistor OFF. * VOUT= VDD-40V
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 15 -1 40
0.4 70 k A
IOFF(2)
4.5 to 6.0
-30
Continued on next page.
No. 4300-11/19
LC86E6032
Continued from preceding page. Parameter Symbol Pins Conditions VDD [V] Pulldown resistor Rpd * S7/T7 to S15T15 * S16 to S23 (With pulldown resistor) Hysteresis voltage VHIS * Ports 0,1 * Port 7 * RES Pin capacitance CP All pins * f=1MHz * Unmeasurement terminals for input are set to VSS level. * Ta= 25C 4.5 to 6.0 10 pF * Output P-channel transistor OFF. * VOUT= 3V * VP= -30V * Output disable 4.5 to 6.0 0.1VDD V 5.0 min 60 Ratings typ 100 max 200 k Unit
4. Serial Input/Output Characteristics at Ta = +10C to +40C , VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Cycle Lowlevel pulse width Highlevel pulse width Cycle tCKCY(1) tCKL(1) SCK0, SCK1 Refer to Figure 5. 4.5 to 6.0 4.5 to 6.0 min 2 1 Ratings typ max tCYC Unit
Input clock
tCKH(1)
4.5 to 6.0
1
Serial clock
tCKCY(2)
SCK0, SCK1
Output clock
Lowlevel pulse width Highlevel pulse width
tCKL(2)
* Use pull-up resistor (1 k) when set to open-drain output. * Refer to Figure 5.
4.5 to 6.0
2
4.5 to 6.0
1/2tCKCY
tCKH(2)
4.5 to 6.0
1/2tCKCY
Serial input
Data set-up time Data hold time Output delay time (Serial clock is extrnal clock.) Output delay time (Serial clock is internal clock.)
tICK tCKI
* SI0, SI1 * SB0, SB1
* Data set-up to SCK0, 1 * Refer to Figure 5.
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
0.1 0.1 7/12tCYC +0.2
s
tCKO(1)
* SO0, SO1 * SB0, SB1
Serial output
* Data hold from SCK0, 1 * Use pull-up resistor (1 k) when set to open-drain output. * Refer to Figure 5. * Data hold from SCK0, 1 * Use pull-up resistor (1 k) when set to open-drain output. * Refer to Figure 5.
tCKO(2)
* SO0, SO1 * SB0, SB1
4.5 to 6.0
1/3tCYC +0.2
No. 4300-12/19
LC86E6032
5. Pulse Input Conditions at Ta = +10C to +40C, VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] High/low-level pulse width tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIL(4) * INT0, INT1 * INT2/T0IN INT3/T0IN (The noise rejection clock selected to 1/1.) * Interrupt acceptable * Timer 0 pulse countable * Interrupt acceptable * Timer 0 pulse countable 4.5 to 6.0 min 1 Ratings typ max tCYC Unit
4.5 to 6.0
2
* Interrupt acceptable INT3/T0IN * Timer 0 pulse (The noise rejection clock selected to 1/64.) countable RES Reset acceptable
4.5 to 6.0
128
4.5 to 6.0
200
s
6. A/D Converter Characteristics at Ta = +10C to +40C, VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Resolution Absolute precision Conversion time N ET tCAD (Note 2) A/D conversion time = 16 x tCYC (ADCR2 = 0) (Note 3) A/D conversion time = 32 x tCYC (ADCR2 = 1) (Note 3) Analog input voltage range Analog port input current VAIN IAINH IAINL AN0 to AN3 VAIN = VDD VAIN = VSS -1 15.68 (tCYC = 0.98 s) 31.36 (tCYC = 0.98 s) VSS 4.5 to 6.0 min Ratings typ 8 1.5 65.28 (tCYC = 4.08 s) 130.56 (tCYC = 4.08 s) VDD 1 V A max bit LSB s Unit
(Note 2) Absolute precision excepts quantizing error (1/2 LSB). (Note 3) The conversion time is the time from execution of the instruction to start conversion to the completion of shifting the A/D converted value to the register.
No. 4300-13/19
LC86E6032
7. Current Drain Characteristics at Ta = +10C to +40C , VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Current drain during basic operation (Note 4) IDDOP(1) VDD * FmCF = 12 MHz for ceramic resonator oscillation. * FsXtal = 32.768 kHz for crystal oscillator. * System clock : 12 MHz side * Internal RC oscillator stopped. * FmCF = 3 MHz for ceramic resonator oscillation. * FsXtal = 32.768 kHz for crystal oscillator. * System clock : 3 MHz side * Internal RC oscillator stopped. * FmCF = 0 Hz (when oscillator stops). * FsXtal = 32.768 kHz for crystal oscillator. * System clock : RC oscillator. * FmCF = 0 Hz (when oscillator stops). * FsXtal = 32.768 kHz for crystal oscillator. * System clock : 32.768 kHz side * Internal RC oscillator stopped. 4.5 to 6.0 min Ratings typ 13 max 26 mA Unit
IDDOP(2)
4.5 to 6.0
6.5
14
IDDOP(3)
4.5 to 6.0
4
10
IDDOP(4)
4.5 to 6.0
3.5
9
Continued on next page.
No. 4300-14/19
LC86E6032
Continued from preceding page. Parameter Symbol Pins Conditions VDD [V] Current drain at HALT mode (Note 4) IDDHALT(1) VDD * HALT mode * FmCF = 12 MHz for ceramic resonator oscillation. * FsXtal = 32.768 kHz for crystal oscillator. * System clock : 12 MHz side * Internal RC oscillator stopped. * HALT mode * FmCF = 3 MHz for ceramic resonator oscillation. * FsXtal = 32.768 kHz for crystal oscillator. * System clock : 3 MHz side * Internal RC oscillator stopped. * HALT mode * FmCF = 0 Hz (when oscillator stops). * FsXtal = 32.768 kHz for crystal oscillator. * System clock : RC oscillator * HALT mode * FmCF = 0 Hz (when oscillator stops). * FsXtal = 32.768 kHz for crystal oscillator. * System clock : 32.768 kHz side * Internal RC oscillator stopped. VDD HOLD mode 4.5 to 6.0 min Ratings typ 5 max 10 mA Unit
IDDHALT(2)
4.5 to 6.0
1.8
4.6
IDDHALT(3)
4.5 to 6.0
400
800
A
IDDHALT(4)
4.5 to 6.0
20
60
Current drain at HOLD mode (Note 4)
IDDHOLD(1)
4.5 to 6.0
0.05
30
IDDHOLD(2)
2.5 to 4.5
0.02
20
(Note 4) The currents of output transistors and pull-up MOS transistors are ignored.
No. 4300-15/19
LC86E6032
Oscillation type 12 MHz ceramic resonator oscillation Supplier Murata Oscillator CSA12.0MTZ CSA12.0MT CST12.0MTW Kyocera 3 MHz ceramic resonator oscillation Kyocera Murata KBR-12.0M CSA3.00MG CST3.00MGW KBR-3.0MS C1 33 pF 33 pF on chip 33 pF 33pF on chip 47 pF 47 pF 33 pF 33 pF C2 33 pF 33 pF
* Both C1 and C2 must use K rank (10%) and SL characteristics. Table 1. Ceramic Resonator Oscillation Guaranteed Constants (Main-clock)
Oscillation type 32.768 kHz crystal oscillation
Supplier Dai Sinku Kyocera
Oscillator DT-38(1TA252E00) KF-38G-13P0200
C3 18 pF 18 pF
C4 18 pF 18 pF
* Both C3 and C4 must use J rank (5%) and CH characteristics. (If high precision is unnecessary, use K rank (10%) and SL characteristics.) Table 2. Crystal Oscillation Guaranteed Constants (Sub-clock) Notes * Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest pattern length. * If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1
CF2
XT1
XT2
C1
CF
C2
C3
X'tal
C4
Main-clock circuit Figure 1 Ceramic Resonator Oscillation
Sub-clock circuit Figure 2 Crystal Oscillation
No. 4300-16/19
LC86E6032
VDD VDD VDD lower limit VDD limit
0V
Power supply Reset time RES Internal RC resonator oscillation tmsCF CF1, CF2 tssXtal XT1,XT2
Operation mode
Unfixed
Reset
Instruction execution mode
< Reset time and oscillation stable time. >
HOLD release signal
Valid
Internal RC resonator oscillation tmsCF CF1, CF2 tssXtal XT1,XT2
Operation mode
HOLD
Instruction execution mode
< HOLD release signal and oscillation stable time. >
Figure 3 Oscillation Stable Time
VDD VDD RRES RES CRES
(Note) (Note) of C the value of be determined that The valuesFix RES and RRES should CRES, RRES such that is time to least 200 s, measured from the resetsure is at reset untill 200s, after moment the power exceeds the VDD lower limit. Power supply has been over inferior
limit of supply voltage.
Figure 4 Reset Circuit No. 4300-17/19
LC86E6032
0.5VDD 0.5VDD
< AC timing point < AC timing point > >
tCKCY tCKL
SCK0 SCK1
VDD VDD
tCKH 1k tICK tCKI
SI0 SI1
tCKO
SO0,SO1 SB0,SB1
50pF
< Timing >
< Test load >
Figure 5 Serial Input/Output Test Conditions
tPIL
tPIH
Figure 6 Pulse Input Timing Conditions
No. 4300-18/19
LC86E6032
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of December, 1998. Specifications and information herein are subject to change without notice.
PS No. 4300-19/19

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